The present invention relates generally to data processing systems and, more particularly, to a receiver circuit having a clock signal input.
Many application-specific integrated circuits (ASICs) presently in use have an external clock signal as an input thereto. A clock signal is a steady stream of timing pulses (e.g., from a crystal oscillator) that synchronize the operations within a data processing system or integrated circuit. For example, the clock rate of a computer essentially determines the maximum operating speed of the computer.
Several embodiments of clock signal output circuitry are in existence. Two such examples are differential Positive Emitter Coupled Logic (PECL) oscillators and Complimentary Metal-Oxide Semiconductor (CMOS) field-effect transistor logic circuitry. Generally speaking, PECL is part of a highly specialized logic family normally used in high speed data transition and transmission applications. PECL oscillators, having differential outputs, generally provide tighter output tolerances but tend to be more expensive than CMOS technology. CMOS logic, on the other hand, is typically less expensive than PECL, and is used in low power applications. Thus, certain circuit designs which are cost sensitive are more amenable to CMOS logic, while other designs which are performance sensitive may be more amenable to PECL.
Another important difference between PECL and CMOS technology is the applicable logic levels used by each. Typically, a CMOS logic circuit has a rail (high state) voltage of approximately 3.3 volts. On the other hand, a PECL logic circuit typically operates with a differential voltage swing which is less than that of a CMOS circuit, approximately 1 volt. It can be seen, therefore, that the difference between the two logic families may present difficulties with regard to the interchangeability of external components, such as oscillators, used in conjunction with a particular design of integrated circuit.
The above discussed and other drawbacks and deficiencies of the prior art are overcome or alleviated by an apparatus for receiving an input signal to an integrated circuit device. In an exemplary embodiment of the invention, the apparatus includes a CMOS receiver configured to receive the input signal and a PECL receiver configured to receive the input signal. The PECL receiver shares a common output node with the CMOS receiver. A receiver selection mechanism is coupled to the CMOS receiver and the PECL receiver, with the receiver selection mechanism alternatively activating or deactivating the CMOS receiver and the PECL receiver.
In a preferred embodiment, a first input terminal and a second input terminal, are configured to receive the input clock signal. A biasing network is connected to said first and said second input terminals which, when activated, provides a bias voltage on the first and second input terminals. The biasing network is activated whenever the PECL receiver is activated. The CMOS receiver is activated by the receiver selection mechanism when the second input terminal is connected to ground, while the PECL receiver is deactivated by the receiver selection mechanism when the second input terminal is connected to ground.